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failIncident: Malware
Scanned: 3 days ago

SystemVerilog and Verilog Formatter

Artifact:
latest
malicious
Top 10k
Beautify SystemVerilog and Verilog code in VSCode through Verible
License: Permissive (MIT)
Published: 4 months ago
Publisher: bmpenuelas
Visit Github
See on Visual Studio Code

SAFE Assessment

Compliance

Licenses
No license compliance issues
Secrets
50 debugging symbols found

Security

Vulnerabilities
No known vulnerabilities detected
Hardening
43 baseline mitigations missing

Threats

Tampering
No evidence of software tampering
Malware
3 malicious components found

INCIDENTS FOR THIS VERSION:

malware
3 months agoReported By: ReversingLabs (Automated)
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... that you can use ReversingLabs’ Spectra Assure platform to perform regular risk assessments of packages you develop in-house?

We recommend continuous software safeness monitoring through CI/CD integrations and pre-release/deployment checks. In addition to basic package information found on this page our platform offers rich reports for developers and DevSecOps that help them remediate all reported issues.