warningRisk: Hardening
Scanned: 5 days ago
SystemVerilog and Verilog Formatter
Beautify SystemVerilog and Verilog code in VSCode through Verible
License: Permissive (MIT)
Published: 8 months ago
Publisher: bmpenuelasSAFE Assessment
Compliance
Licenses
No license compliance issues
Secrets
50 debugging symbols found
Security
Vulnerabilities
No known vulnerabilities detected
Hardening
43 baseline mitigations missing
Threats
Tampering
No evidence of software tampering
Malware
No evidence of malware inclusion